Structures and methods for trench isolation

US11894381B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Kuan-Jung Chen · Tainan, TW
• Tsung-Lin Lee · Hsinchu, TW
• Chung-Ming Lin · Zhongpu, TW
• Wen-Chih Chiang · Hsinchu, TW
• Cheng-Hung Wang · Jinshanmian, TW

Key dates

• Filing date: Oct 28, 2019
• Grant date: Feb 6, 2024
• Expiry date: Oct 28, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/01
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Structures and methods for trench isolation are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, a buried layer arranged over the insulation layer, and a trench extending downward from an upper surface of the buried layer and terminating in the handle layer. The dielectric layer is located on a bottom surface of the trench and contacting the handle layer. The polysilicon region is located in the trench and contacting the dielectric layer.