Enhanced auxiliary memory mapped interface test systems and methods
US11899550B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2021 |
| Grant date | Feb 13, 2024 |
| Priority date | — |
| Expiry date | Jan 28, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, an enhanced auxiliary interface test system comprises a load board, testing electronics, controller, and memory mapped interface. The load board is configured to couple with a plurality of devices under test (DUTs). The testing electronics is configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board. The controller is configured to direct testing of the DUTs, wherein the controller is coupled to the testing electronics. The memory mapped interface is configured to implement multiple paths to access a central processing unit (CPU) on the controller and enable testing of multiple DUTs in parallel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.