Partial block handling in a non-volatile memory device
US11901014B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2022 |
| Grant date | Feb 13, 2024 |
| Priority date | — |
| Expiry date | Aug 5, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.