Fast open block erase in non-volatile memory structures
US11901016B2 · kind B2 · utility
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Key dates
| Filing date | Apr 29, 2022 |
| Grant date | Feb 13, 2024 |
| Priority date | — |
| Expiry date | Aug 27, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for performing an erase operation of a partially programmed memory block of a non-volatile memory structure. The method comprises: (1) applying an erase voltage bias level to a channel region of the memory block, (2) applying a word line voltage level to all programmed word line(s) of the memory block, (3) applying a “float” condition to all unprogrammed word line(s) of the memory block, and (4) applying an erase verify operation to all word line(s) of the memory block, wherein the “float” condition comprises omitting application of the word line voltage to the unprogrammed word line(s).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.