Inventor · Sunnyvale, CA, US

Jiacen Guo

27Patents
1h-index
20Co-inventors
46Inventor score

Filing activity: Nov 16, 2021 → Jul 27, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US11942157B2 Variable bit line bias for nonvolatile memory Electricity 2 Active
US11955184B2 Memory cell group read with compensation for different programming speeds Physics 1 Active
US11923019B2 Data retention reliability Physics 1 Active
US11894072B2 Two-side staircase pre-charge in sub-block mode of three-tier non-volatile memory architecture Physics 1 Active
US12205654B2 MLC programming techniques in a memory device Physics 0 Active
US11848059B2 Techniques for erasing the memory cells of edge word lines Physics 0 Active
US11901016B2 Fast open block erase in non-volatile memory structures Electricity 0 Active
US11862249B2 Non-volatile memory with staggered ramp down at the end of pre-charging Electricity 0 Active
US12394489B2 In-place write techniques without erase in a memory device Physics 0 Active
US11972806B2 Read techniques to reduce read errors in a memory device Physics 0 Active
US11881271B2 Non-volatile memory with engineered channel gradient Physics 0 Active
US12112812B2 Non-volatile memory with early dummy word line ramp down after precharge Physics 0 Active
US12431203B2 Memory program-verify with adaptive sense time based on row location Physics 0 Active
US12142315B2 Low power multi-level cell (MLC) programming in non-volatile memory structures Physics 0 Active
US11972813B2 Systems and methods for adapting sense time Physics 0 Active
US11972820B2 Non-volatile memory with tier-wise ramp down after program-verify Physics 0 Active
US12119065B2 Non-volatile memory with zoned control for limiting programming for different groups of non-volatile memory cells Electricity 0 Active
US11862260B2 Audit techniques for read disturb detection in an open memory block Electricity 0 Active
US11837292B2 String or block or die level dependent source line voltage for neighbor drain side select gate interference compensation Physics 0 Active
US12229415B2 Hole channel pre-charge to enable large-volume in-place data sanitization of non-volatile memory Physics 0 Active
US12100461B2 Non-volatile memory with suspension period during programming Physics 0 Active
US12112800B2 High speed multi-level cell (MLC) programming in non-volatile memory structures Physics 0 Active
US12254931B2 Three-bit-per-cell programming using a four-bit-per-cell programming algorithm Physics 0 Active
US12176037B2 Non-volatile memory with different word line to word line pitches Physics 0 Active
US12243591B2 In-place write techniques without erase in a memory device Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.