Self-aligned scheme for semiconductor device and method of forming the same
US11901228B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2021 |
| Grant date | Feb 13, 2024 |
| Priority date | — |
| Expiry date | Oct 28, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76883
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a method includes forming a first conductive feature in a first inter-metal dielectric (IMD) layer; depositing a blocking film over and physically contacting the first conductive feature; depositing a first dielectric layer over and physically contacting the first IMD layer; depositing a second dielectric layer over and physically contacting the first dielectric layer; removing the blocking film; depositing an etch stop layer over any physically contacting the first conductive feature and the second dielectric layer; forming a second IMD layer over the etch stop layer; etching an opening in the second IMD layer and the etch stop layer to expose the first conductive feature; and forming a second conductive feature in the opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.