Integrated circuit structure and fabrication method thereof
US11901318B2 · kind B2 · utility
1Cited by
0References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2021 |
| Grant date | Feb 13, 2024 |
| Priority date | — |
| Expiry date | Jun 6, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit structure includes a substrate with a circuit region thereon and a copper interconnect structure disposed on the substrate. The copper interconnect structure includes an uppermost copper layer covered by a dielectric layer. An aluminum pad layer is provided on the dielectric layer. A metal layer is provided on the circuit region and is located between the uppermost copper layer and the aluminum pad layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.