Microelectronic package with three-dimensional (3D) monolithic memory die
US11901347B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | May 29, 2020 |
| Grant date | Feb 13, 2024 |
| Priority date | — |
| Expiry date | May 31, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments may relate to a microelectronic package. The microelectronic package may include a memory die with: a first memory cell at a first layer of the memory die; a second memory cell at a second layer of the memory die; and a via in the memory die that communicatively couples an active die with a package substrate of the microelectronic package. Other embodiments may be described or claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.