Conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devices
US11903183B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2020 |
| Grant date | Feb 13, 2024 |
| Priority date | — |
| Expiry date | Mar 21, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and apparatus including conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devices. One memory device comprises arrays of vertically stacked memory cells, having multiple multi-direction conductive lines arrays of vertically stacked memory cells, including a vertical stack of layers formed from repeating iterations of a group of layers, the group of layers comprising: a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer, the second dielectric material layer having a conductive line formed in a horizontal plane therein, and the vertical stack of layers having multiple multi-direction conductive lines in an interconnection region with a first portion of the interconnection region formed in an array region and a second portion formed in a conductive line contact region that is spaced from the array region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.