Sheng-Wei Yang
28Patents
4h-index
36Co-inventors
63Inventor score
Filing activity: May 11, 1993 → Sep 19, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6946359B2 | Method for fabricating trench isolations with high aspect ratio | Electricity | 13 | Expired |
| US5320792A | Process for the preparation of LAS ceramic sintered bodies | Chemistry; Metallurgy | 7 | Expired |
| US9041099B2 | Single-sided access device and fabrication method thereof | Electricity | 6 | Active |
| US9117759B2 | Methods of forming bulb-shaped trenches in silicon | Electricity | 5 | Active |
| US7074700B2 | Method for isolation layer for a vertical DRAM | Electricity | 4 | Expired |
| US10811365B2 | Semiconductor devices having crack-inhibiting structures | Electricity | 3 | Active |
| US8415728B2 | Memory device and method of fabricating the same | Electricity | 3 | Active |
| US10784212B2 | Semiconductor devices having crack-inhibiting structures | Emerging Cross-Sectional Technologies | 3 | Active |
| US10854514B2 | Microelectronic devices including two contacts | Electricity | 2 | Active |
| US6897108B2 | Process for planarizing array top oxide in vertical MOSFET DRAM arrays | Electricity | 2 | Expired |
| US11488981B2 | Array of vertical transistors and method used in forming an array of vertical transistors | Electricity | 2 | Active |
| US8426925B2 | Memory device and method of fabricating the same | Electricity | 2 | Active |
| US8658538B2 | Method of fabricating memory device | Electricity | 1 | Active |
| US11444037B2 | Semiconductor devices having crack-inhibiting structures | Emerging Cross-Sectional Technologies | 1 | Active |
| US9419001B1 | Method for forming cell contact | Electricity | 1 | Active |
| US8901631B2 | Vertical transistor in semiconductor device and method for fabricating the same | Electricity | 1 | Active |
| US6927123B2 | Method for forming a self-aligned buried strap in a vertical memory cell | Electricity | 1 | Expired |
| US10388564B2 | Method for fabricating a memory device having two contacts | Electricity | 1 | Active |
| US11903183B2 | Conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devices | Electricity | 0 | Active |
| US9012303B2 | Method for fabricating semiconductor device with vertical transistor structure | Electricity | 0 | Active |
| US11848282B2 | Semiconductor devices having crack-inhibiting structures | Emerging Cross-Sectional Technologies | 0 | Active |
| US8334196B2 | Methods of forming conductive contacts in the fabrication of integrated circuitry | Electricity | 0 | Active |
| US12336288B2 | Array of vertical transistors and method used in forming an array of vertical transistors | Electricity | 0 | Active |
| US10891410B1 | User-defined rule engine | Emerging Cross-Sectional Technologies | 0 | Active |
| US8647988B2 | Memory device and method of fabricating the same | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.