Processor with multiple op cache pipelines
US11907126B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Dec 9, 2020 |
| Grant date | Feb 20, 2024 |
| Priority date | — |
| Expiry date | Dec 9, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor employs a plurality of op cache pipelines to concurrently provide previously decoded operations to a dispatch stage of an instruction pipeline. In response to receiving a first branch prediction at a processor, the processor selects a first op cache pipeline of the plurality of op cache pipelines of the processor based on the first branch prediction, and provides a first set of operations associated with the first branch prediction to the dispatch queue via the selected first op cache pipeline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.