Memory system design using buffer(s) on a mother board
US11907139B2 · kind B2 · utility
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16References
18Claims
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Key dates
| Filing date | Dec 20, 2022 |
| Grant date | Feb 20, 2024 |
| Priority date | — |
| Expiry date | Dec 20, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.