Physically secure memory partitioning
US11907559B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2022 |
| Grant date | Feb 20, 2024 |
| Priority date | — |
| Expiry date | Aug 26, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1052
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory, a secure-access circuit, a plain-access circuit, and protection hardware. The memory includes at least a secure-storage partition assigned a first address range and a plain-storage partition assigned a second address range, disjoint from the first address range. The secure-access circuit is configured to access the secure-storage partition by generating addresses in the first address range. The plain-access circuit is configured to access the plain-storage partition by generating addresses in the second address range. The protection hardware is configured to prevent the plain-access circuit from accessing the first address range assigned to the secure-storage partition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.