Multi-die memory device with peak current reduction
US11908812B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2021 |
| Grant date | Feb 20, 2024 |
| Priority date | — |
| Expiry date | Aug 1, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1434
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory device including a substrate including a substrate contact pad. The memory device includes a first memory die including a first power supply contact pad electrically coupled to the substrate contact pad and a first power supply circuit on the first memory die. The first memory die further includes a first electrostatic discharge (ESD) power clamp contact pad electrically coupled to the substrate contact pad and a first ESD power clamp circuit on the first memory die. The memory device further includes a second memory die including a second power supply contact pad electrically coupled to the substrate contact pad and a second power supply circuit on the second memory die and a second ESD power clamp contact pad electrically coupled to a second ESD power clamp circuit on the second memory die, wherein the second ESD power clamp contact pad is electrically disconnected from the substrate contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.