Memory side cache request handling
US11914516B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2022 |
| Grant date | Feb 27, 2024 |
| Priority date | — |
| Expiry date | Aug 30, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
System and techniques for memory side cache request handling are described herein. When a memory request is received, a cache set for the memory request is determined. Here, the cache set has multiple ways and each way corresponds to a cache line. It can be detected that a way of the multiple ways is not ready for the memory request. In this case, a representation of the memory request is stored in a queue of multiple queues based on an interface upon which the memory request was received and the present ways of the cache set. Entries from the multiple queues can be dequeued in a defined order to determine a next memory request to process. The defined order gives priority to memory requests for a present way and then for external over internal requests.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.