Parallel access in a memory array
US11915740B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2022 |
| Grant date | Feb 27, 2024 |
| Priority date | — |
| Expiry date | Aug 31, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for parallel access in a memory array are described. A set of memory cells of a memory device may be associated with an array of conductive structures, where such structures may be coupled using a set of transistors or other switching components that are activated by a first driver. The set of memory cells may be divided into two or more subsets of memory cells, where each subset may be associated with a respective second driver for driving access currents through memory cells of the subset. Two or more of such second drivers may operate concurrently, which may support distributing current or distributing associated circuit structures across a different footprint of the memory device than other different implementations with a single such second driver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.