Leveraging processing-in-memory (PIM) resources to expedite non-PIM instructions executed on a host
US11921634B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2021 |
| Grant date | Mar 5, 2024 |
| Priority date | — |
| Expiry date | May 5, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30043
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Leveraging processing-in-memory (PIM) resources to expedite non-PIM instructions executed on a host is disclosed. In an implementation, a memory controller identifies a first write instruction to write first data to a first memory location, where the first write instruction is not a processing-in-memory (PIM) instruction. The memory controller then writes the first data to a first PIM register. Opportunistically, the memory controller moves the first data from the first PIM register to the first memory location. In another implementation, a memory controller identifies a first memory location associated with a first read instruction, where the first read instruction is not a processing-in-memory (PIM) instruction. The memory controller identifies that a PIM register is associated with the first memory location. The memory controller then reads, in response to the first read instruction, first data from the PIM register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.