Data buffering operation of three-dimensional memory device with static random-access memory
US11922058B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2021 |
| Grant date | Mar 5, 2024 |
| Priority date | — |
| Expiry date | Jun 2, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2245
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of a three-dimensional (3D) memory device and a method of operating the 3D memory device are provided. The 3D memory device includes an array of 3D NAND memory cells, an array of static random-access memory (SRAM) cells, and a peripheral circuit. The array of SRAM cells and the peripheral circuit arranged at one side are bonded with the array of 3D NAND memory cells at another side to form a chip. Data is received from a host through the peripheral circuit, buffered in the array of SRAM cells, and transmitted from the array of SRAM cells to the array of 3D NAND memory cells. The data is programmed into the array of 3D NAND memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.