Data retention reliability
US11923019B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2022 |
| Grant date | Mar 5, 2024 |
| Priority date | — |
| Expiry date | Jul 31, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides for improving data retention reliability. During a programming operation associated with a memory cell, after the memory cell passes verification of a first verification voltage level, a second verification voltage level can be applied to the memory cell. Based on a comparison of the voltage in the memory cell with the second verification voltage level, a bit line voltage may be applied. Based on the applied bit line voltage, fast bits associated with the memory cell can be upshifted to an upper portion of a final voltage distribution associated with the programming operation. Upshifting the fast bits counteracts the downshifting effect in a final voltage distribution that may be caused by charge leakage or electron loss.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.