Three-dimensional memory devices and memory system
US11929119B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2021 |
| Grant date | Mar 12, 2024 |
| Priority date | — |
| Expiry date | Oct 16, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, and a first bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells. The second semiconductor structure includes a first peripheral circuit of the array of memory cells. The first peripheral circuit includes a first transistor. A third semiconductor structure includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor. The first semiconductor structure, the second semiconductor structure, and the third semiconductor structure are stacked over one another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.