Layout techniques and optimization for power transistors
US11929408B2 · kind B2 · utility
0Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 14, 2020 |
| Grant date | Mar 12, 2024 |
| Priority date | — |
| Expiry date | Mar 7, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/471
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various embodiments are disclosed for improved and structurally optimized transistors, such as RF power amplifier transistors. A transistor may include a drain metal portion raised from a surface of a substrate, a drain metal having a notched region, a gate manifold body with angled gate tabs extending from the gate manifold, and/or a source-connected shielding. The transistor may include a high-electron-mobility transistor (HEMT), a gallium nitride (GaN)-on-silicon transistor, a GaN-on-silicon-carbide transistor, or other type of transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.