Three-dimensional memory devices having polysilicon layer and bonded semiconductor structures and methods for forming the same
US11935596B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2021 |
| Grant date | Mar 19, 2024 |
| Priority date | — |
| Expiry date | Nov 21, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells, a first peripheral circuit of the array of memory cells, and a polysilicon layer between the array of memory cells and the first peripheral circuit. The first peripheral circuit includes a first transistor. The second semiconductor structure includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.