Patent · US Active

Method with stealth dicing process for fabricating MEMS semiconductor chips

US11939216B2 · kind B2 · utility

0Cited by

3References

14Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Andre Brockmeier · Villach, AT
Stephan Helbig · Regensburg, DE
Adolf Koller · Regensburg, DE

Key dates

Filing date	Mar 1, 2021
Grant date	Mar 26, 2024
Priority date	—
Expiry date	Jun 10, 2042

Classification

Technology area (CPC B)Performing Operations; Transporting
CPC primaryB81C2201/0143
WIPO fieldMicro-structural and nano-technology
WIPO sectorChemistry

Abstract

A method includes producing a semiconductor wafer. The semiconductor wafer includes a plurality of microelectromechanical system (MEMS) semiconductor chips, wherein the MEMS semiconductor chips have MEMS structures arranged at a first main surface of the semiconductor wafer, a first semiconductor material layer arranged at the first main surface, and a second semiconductor material layer arranged under the first semiconductor material layer, wherein a doping of the first semiconductor material layer is greater than a doping of the second semiconductor material layer. The method further includes removing the first semiconductor material layer in a region between adjacent MEMS semiconductor chips. The method further includes applying a stealth dicing process from the first main surface of the semiconductor wafer and between the adjacent MEMS semiconductor chips.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.