Selective management of erase operations in memory devices that enable suspend commands
US11942159B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2022 |
| Grant date | Mar 26, 2024 |
| Priority date | — |
| Expiry date | Sep 29, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory array of memory cells and control logic operatively coupled with the memory array. The control logic is to perform operations including: initiating a true erase sub-operation by causing an erase pulse to be applied to one or more sub-blocks of the memory array; tracking, a number of suspend commands received from a processing device during time periods that a memory line of the memory array is caused to ramp towards an erase voltage of the erase pulse; causing, in response to receiving each suspend command, the true erase sub-operation to be suspended to enable performing a non-erase memory operation; and in response to the number of suspend commands satisfying a threshold criterion, alerting the processing device to terminate sending suspend commands until after completion of the true erase sub-operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.