Process of forming an electronic device including a doped gate electrode
US11942326B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2020 |
| Grant date | Mar 26, 2024 |
| Priority date | — |
| Expiry date | Jun 15, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/64
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process to form a HEMT can have a gate electrode layer that initially has a plurality of spaced-apart doped regions. In an embodiment, any of the spaced-apart doped regions can be formed by depositing or implanting p-type dopant atoms. After patterning, the gate electrode can include an n-type doped region over the p-type doped region. In another embodiment a barrier layer can underlie the gate electrode and include a lower film with a higher Al content and thinner than an upper film. In a further embodiment, a silicon nitride layer can be formed over the gate electrode layer and can help to provide Si atoms for the n-type doped region and increase a Mg:H ratio within the gate electrode. The HEMT can have good turn-on characteristics, low gate leakage when in the on-state, and better time-dependent breakdown as compared to a conventional HEMT.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.