Peter Moens
64Patents
5h-index
46Co-inventors
68Inventor score
Filing activity: Jan 7, 2005 → Jun 23, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7709889B2 | Semiconductor device with improved breakdown properties and manufacturing method thereof | Electricity | 15 | Active |
| US9673311B1 | Electronic device including a multiple channel HEMT | Electricity | 13 | Active |
| US7723800B2 | Deep trench isolation for power semiconductors | Electricity | 13 | Active |
| US9741840B1 | Electronic device including a multiple channel HEMT and an insulated gate electrode | Electricity | 10 | Active |
| US7804670B2 | Hybrid ESD clamp | Electricity | 6 | Active |
| US8115273B2 | Deep trench isolation structures in integrated semiconductor devices | Electricity | 5 | Active |
| US10797168B1 | Electronic device including a high electron mobility transistor that includes a barrier layer having different portions | Electricity | 5 | Active |
| US7667270B2 | Double trench for isolation of semiconductor devices | Electricity | 5 | Active |
| US9343528B2 | Process of forming an electronic device having a termination region including an insulating region | Electricity | 4 | Active |
| US9728629B1 | Electronic device including a polycrystalline compound semiconductor layer and a process of forming the same | Electricity | 4 | Active |
| US9070705B2 | HEMT semiconductor device and a process of forming the same | Electricity | 4 | Active |
| US10644127B2 | Process of forming an electronic device including a transistor structure | Electricity | 4 | Active |
| US9219138B2 | Semiconductor device having localized charge balance structure and method | Electricity | 4 | Active |
| US7608510B2 | Alignment of trench for MOS | Electricity | 4 | Active |
| US7915155B2 | Double trench for isolation of semiconductor devices | Electricity | 4 | Active |
| US10269947B1 | Electronic device including a transistor including III-V materials and a process of forming the same | Electricity | 4 | Active |
| US9842923B2 | Ohmic contact structure for semiconductor device and method | Electricity | 3 | Active |
| US9287371B2 | Semiconductor device having localized charge balance structure and method | Electricity | 3 | Active |
| US10818787B1 | Electronic device including a high electron mobility transistor including a gate electrode and a dielectric film | Electricity | 3 | Active |
| US9245736B2 | Process of forming a semiconductor wafer | Electricity | 3 | Active |
| US10680094B2 | Electronic device including a high electron mobility transistor including a gate electrode | Electricity | 3 | Active |
| US7989886B2 | Alignment of trench for MOS | Electricity | 2 | Active |
| US9324784B2 | Electronic device having a termination region including an insulating region | Electricity | 2 | Active |
| US9269789B2 | Method of forming a high electron mobility semiconductor device and structure therefor | Electricity | 2 | Active |
| US9960265B1 | III-V semiconductor device and method therefor | Electricity | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.