Reduced interfacial area III-nitride material semiconductor structures
US11942518B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2021 |
| Grant date | Mar 26, 2024 |
| Priority date | — |
| Expiry date | May 26, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/343
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor structures and devices in III-nitride materials are described herein, including material structures comprising III-nitride material regions (e.g., gallium nitride material regions). In certain cases, the material structures comprise substrates having relatively high electrical conductivities. In other cases, the material structures comprise substrates having relatively high resistivities. Certain embodiments include one or more features that reduce the degree to which thermal runaway occurs, which can enhance device performance including at elevated flange temperatures. Some embodiments include one or more features that reduce the degree of capacitive coupling exhibited during operation. For example, in some embodiments, relatively thick III-nitride material regions and/or relatively small ohmic contacts are employed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.