Packet routing between memory devices and related apparatuses, methods, and memory systems
US11947798B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 24, 2021 |
| Grant date | Apr 2, 2024 |
| Priority date | — |
| Expiry date | Nov 5, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/205
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Packet routing between memory devices and related apparatuses, methods, and memory systems are disclosed. An apparatus of a memory device includes a memory controller, two or more memory interfaces, packet relay logic configured to control the two or more memory interfaces, and a switch. The switch is configured to pass a received packet received through a first memory interface of the two or more memory interfaces to the memory controller responsive to a determination that the received packet indicates the memory device as a destination of the received packet. The switch is also configured to pass the received packet through a second memory interface of the two or more memory interfaces toward an other memory device responsive to a determination that the received packet indicates the other memory device as the destination of the received packet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.