Throttling hull shaders based on tessellation factors in a graphics pipeline
US11948251B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 26, 2022 |
| Grant date | Apr 2, 2024 |
| Priority date | — |
| Expiry date | Oct 26, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/504
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system includes hull shader circuitry that launches thread groups including one or more primitives. The hull shader circuitry also generates tessellation factors that indicate subdivisions of the primitives. The processing system also includes throttling circuitry that estimates a primitive launch time interval for the domain shader based on the tessellation factors and selectively throttles launching of the thread groups from the hull shader circuitry based on the primitive launch time interval of the domain shader and a hull shader latency. In some cases, the throttling circuitry includes a first counter that is incremented in response to launching a thread group from the buffer and a second counter that modifies the first counter based on a measured latency of the domain shader.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.