Methods for tuning command/address bus timing and memory devices and memory systems using the same
US11948661B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2021 |
| Grant date | Apr 2, 2024 |
| Priority date | — |
| Expiry date | Jun 21, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices, systems including memory devices, and methods of operating memory devices are described, in which clock trees can be separately optimized to provide a coarse alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal), and/or in which individual memory devices can be isolated for fine-tuning of device-specific alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal). Moreover, individual memory devices can be isolated for fine-tuning of device-specific equalization of a command/address signal (and/or a chip select signal or other control signal).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.