Semiconductor device, integrated circuit and methods of manufacturing the same
US11948941B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2021 |
| Grant date | Apr 2, 2024 |
| Priority date | — |
| Expiry date | Jul 9, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a gate layer, a channel material layer, a first dielectric layer and source/drain terminals. The gate layer is disposed over a substrate. The channel material layer is disposed over the gate layer, where a material of the channel material layer includes a first low dimensional material. The first dielectric layer is between the gate layer and the channel material layer. The source/drain terminals are in contact with the channel material layer, where the channel material layer is at least partially disposed between the source/drain terminals and over the gate layer, and the gate layer is disposed between the substrate and the source/drain terminals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.