Integrated circuit package with voltage droop mitigation
US11950358B1 · kind B1 · utility
1Cited by
1References
20Claims
0Family size
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Key dates
| Filing date | Jun 24, 2021 |
| Grant date | Apr 2, 2024 |
| Priority date | — |
| Expiry date | Jul 27, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L25/0657
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device system comprises an integrated circuit (IC) die. The IC die is configured to operate in a first operating mode during a first period, and a second operating mode during a second period. The first period is associated with enabling an element of the IC die and a first amount of voltage droop. The second period occurs after the first period and is associated with a second amount of voltage droop. The second amount of voltage droop is less than the first amount of voltage droop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.