Spatial tiling of compute arrays with shared control
US11954580B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2020 |
| Grant date | Apr 9, 2024 |
| Priority date | — |
| Expiry date | Oct 16, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N5/046
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a method for machine learning acceleration includes receiving, by a shared controller of a tensor processor cluster that includes multiple tensor processors, a multi-cycle instruction, determining, based on the instruction, a sequence of vector operations to be executed by the tensor processors and address information usable to determine a respective spatial partition of an input tensor on which each tensor processor is to operate when performing each vector operation. The method also includes, for each vector operation in the sequence, generating, based on the address information, a common address offset, relative to a respective base address associated with each tensor processor, at which each tensor processor is to retrieve the respective spatial partition on which the tensor processor is to operate, multicasting the common address offset to the tensor processors, and controlling the tensor processors to execute the vector operation in parallel and in lock step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.