Low stress asymmetric dual side module
US11955412B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2022 |
| Grant date | Apr 9, 2024 |
| Priority date | — |
| Expiry date | Sep 6, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/73265
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.