Dual metal gate structure having portions of metal gate layers in contact with a gate dielectric
US11955532B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2020 |
| Grant date | Apr 9, 2024 |
| Priority date | — |
| Expiry date | Jul 3, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0149
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a semiconductor substrate comprising an N well region having a semiconductor fin protruding therefrom. A trench isolation layer is on the semiconductor substrate around the semiconductor fin, wherein the semiconductor fin extends above the trench isolation layer. A gate dielectric layer is over the semiconductor fin. A conductive layer is over the gate dielectric layer over the semiconductor fin, the conductive layer comprising titanium, nitrogen and oxygen. A P-type metal gate layer is over the conductive layer over the semiconductor fin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.