Semiconductor memory device and fabrication method thereof
US11955565B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2021 |
| Grant date | Apr 9, 2024 |
| Priority date | — |
| Expiry date | Jul 13, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
A semiconductor memory device includes a substrate; a control gate disposed on the substrate; a source diffusion region disposed in the substrate and on a first side of the control gate; a select gate disposed on the source diffusion region, wherein the select gate has a recessed top surface; a charge storage structure disposed under the control gate; a first spacer disposed between the select gate and the control gate and between the charge storage structure and the select gate; a wordline gate disposed on a second side of the control gate opposite to the select gate; a second spacer between the wordline gate and the control gate; and a drain diffusion region disposed in the substrate and adjacent to the wordline gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.