Electronic devices comprising reduced charge confinement regions in storage nodes of pillars and related methods
US11956954B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2020 |
| Grant date | Apr 9, 2024 |
| Priority date | — |
| Expiry date | Jun 16, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic device comprises a stack of alternating dielectric materials and conductive materials, a pillar region extending vertically through the stack, an oxide material within the pillar region and laterally adjacent to the dielectric materials and the conductive materials of the stack, and a storage node laterally adjacent to the oxide material and within the pillar region. A charge confinement region of the storage node is in horizontal alignment with the conductive materials of the stack. A height of the charge confinement region in a vertical direction is less than a height of a respective, laterally adjacent conductive material of the stack in the vertical direction. Related methods and systems are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.