Apparatus and methods employing a shared read post register file
US11960897B2 · kind B2 · utility
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21Claims
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Key dates
| Filing date | Jul 30, 2021 |
| Grant date | Apr 16, 2024 |
| Priority date | — |
| Expiry date | Jul 30, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some implementations, a processor includes a plurality of parallel instruction pipes, a register file includes at least one shared read port configured to be shared across multiple pipes of the plurality of parallel instruction pipes. Control logic controls multiple parallel instruction pipes to read from the at least one shared read port. In certain examples, the at least one shared register file read port is coupled as a single read port for one of the parallel instruction pipes and as a shared register file read port for a plurality of other parallel instruction pipes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.