Semiconductor device package having multi-layer molding compound and method
US11961778B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Sep 27, 2021 |
| Grant date | Apr 16, 2024 |
| Priority date | — |
| Expiry date | Jun 11, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3862
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device package includes a substrate having a top planar surface and a first semiconductor die electrically connected to the top planar surface of the substrate. The first semiconductor die and substrate define a tunnel and a first molding compound encapsulates the first semiconductor die and fills the tunnel. A second molding compound that is separate and distinct from the first molding compound is mounted on a top surface of the first molding compound. The first molding, when in a flowable state, has a viscosity that is lower than a viscosity of the second molding compound when it is in a flowable state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.