Patent · US Active

Bitcell architecture with time-multiplexed ports

US11967365B2 · kind B2 · utility

0Cited by

1References

20Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Yew Keong Chong · Austin, US
Bikas Maiti · Austin, US
Venu Anantuni · Austin, US
Martin Jay Kinkade · Austin, US

Key dates

Filing date	Jun 10, 2020
Grant date	Apr 23, 2024
Priority date	—
Expiry date	Jun 10, 2040

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/419
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Various implementations described herein are related to a device having a memory cell with logic that is configured to store data and passgates that are configured to access the data stored in the logic. The device may include a first number of input-output ports that are time-multiplexed with the passgates so as to increase the first number of input-output ports to a second number of input-output ports that is greater than the first number of input-output ports.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.