Gate structures in transistor devices and methods of forming same
US11967504B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 22, 2021 |
| Grant date | Apr 23, 2024 |
| Priority date | — |
| Expiry date | Mar 30, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes removing a first dummy gate structure to form a recess around a first nanostructure and a second nanostructure; depositing a sacrificial layer in the recess with a flowable chemical vapor deposition (CVD); and patterning the sacrificial layer to leave a portion of the sacrificial layer between the first nanostructure and the second nanostructure. The method further include depositing a first work function metal in first recess; removing the first work function metal and the portion of the sacrificial layer from the recess; depositing a second work function metal in the recess, wherein the second work function metal is of an opposite type than the first work function metal; and depositing a fill metal over the second work function metal in the recess.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.