On-product overlay targets
US11967535B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2021 |
| Grant date | Apr 23, 2024 |
| Priority date | — |
| Expiry date | Oct 27, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54426
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A product includes a semiconductor substrate, with at least first and second thin-film layers disposed on the substrate and patterned to define a matrix of dies, which are separated by scribe lines and contain active areas circumscribed by the scribe lines. A plurality of overlay targets are formed in the first and second thin-film layers within each of the active areas, each overlay target having dimensions no greater than 10 μm×10 μm in a plane parallel to the substrate. The plurality of overlay targets include a first linear grating formed in the first thin-film layer and having a first grating vector, and a second linear grating formed in the second thin-film layer, in proximity to the first linear grating, and having a second grating vector parallel to the first grating vector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.