Three-dimensional memory device containing on-pitch drain select level structures and methods of making the same
US11968825B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2020 |
| Grant date | Apr 23, 2024 |
| Priority date | — |
| Expiry date | Nov 4, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A three-dimensional memory device includes an alternating stack of insulating layers and word-line-level electrically conductive layers located over a substrate, and a vertical layer stack located over the alternating stack, the vertical layer stack including an insulating cap layer, drain select electrodes, and a drain-select-level insulating layer. The drain select electrodes are laterally spaced apart from each other by drain-select-level isolation structures. Memory stack structures including a respective vertical semiconductor channel and a respective memory film vertically extend through the alternating stack and the vertical layer stack. Each of the vertical semiconductor channels includes a word-line-level semiconductor channel portion extending through the alternating stack, a connection channel portion contacting a top end of the word-line-level semiconductor channel, and a drain-select-level semiconductor channel portion vertically extending through the vertical layer stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.