Semiconductor arrangements
US11973065B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 21, 2022 |
| Grant date | Apr 30, 2024 |
| Priority date | — |
| Expiry date | Oct 30, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M7/003
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor arrangement includes at least two switching devices of a first type electrically coupled in parallel between first and second terminals, and at least two switching devices of a second type electrically coupled in parallel between the second terminal and a third terminal. One first diode is electrically coupled in parallel to each switching device of the first type. One second diode is electrically coupled in parallel to each switching device of the second type. The switching devices are arranged in a power semiconductor module having first and second longitudinal sides and first and second narrow sides. The first type switching devices and first diodes are arranged alternatingly in one row along the first longitudinal side. The second type switching devices and second diodes are arranged alternatingly in another row along the second longitudinal side. An axis of symmetry that extends perpendicular to the first and second narrow sides.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.