Synchronous wired-or ACK status for memory with variable write latency
US11973153B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2021 |
| Grant date | Apr 30, 2024 |
| Priority date | — |
| Expiry date | Aug 18, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.