Microelectronic devices with dopant extensions near a GIDL region below a tier stack, and related methods and systems
US11974430B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2021 |
| Grant date | Apr 30, 2024 |
| Priority date | — |
| Expiry date | Mar 24, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/10
Abstract
A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. At least one pillar, comprising a channel material, extends through the stack structure. A source region, below the stack structure, comprises a doped material. A vertical extension of the doped material protrudes upward to an interface with the channel material at elevation within the stack structure (e.g., an elevation proximate or laterally overlapping in elevation at least one source-side GIDL region). The microelectronic device structure may be formed by a method that includes forming a lateral opening through cell materials of the pillar, recessing the channel material to form a vertical recess, and forming the doped material in the vertical recess. Additional microelectronic devices are also disclosed, as are related methods and electronic systems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.