Patent · US Active

Utilizing structured sparsity in systolic arrays

US11977885B2 · kind B2 · utility

1Cited by

2References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Subramaniam Maiyuran · Citrus, US
Jorge Parra · Cameron Park, US
Ashutosh Garg · Sunnyvale, US
Chandra Gurram · Folsom, US
Chunhui Mei · San Diego, US
Durgesh Borkar · Folsom, US
Shubra Marwaha · Folsom, US
Supratim Pal · Bengaluru, IN
Varghese George · Folsom, US
Wei Xiong · Madison, US
Yan Li · Milpitas, US
Yongsheng Liu · Hubei, CN
Dipankar Das · Pune, IN
Sasikanth Avancha · Bengaluru, IN
Dharma Teja Vooturi · Jagtial, IN
Naveen Mellempudi · Kanchinakote, IN

Key dates

Filing date	Nov 30, 2020
Grant date	May 7, 2024
Priority date	—
Expiry date	Aug 14, 2042

Classification

Technology area (CPC G)Physics
CPC primaryG06F17/16
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An apparatus to facilitate utilizing structured sparsity in systolic arrays is disclosed. The apparatus includes a processor comprising a systolic array to receive data from a plurality of source registers, the data comprising unpacked source data, structured source data that is packed based on sparsity, and metadata corresponding to the structured source data; identify portions of the unpacked source data to multiply with the structured source data, the portions of the unpacked source data identified based on the metadata; and output, to a destination register, a result of multiplication of the portions of the unpacked source data and the structured source data.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.