Forming contact holes with controlled local critical dimension uniformity
US11978631B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2020 |
| Grant date | May 7, 2024 |
| Priority date | — |
| Expiry date | Nov 28, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32055
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a device includes forming a hole pattern in a resist layer disposed over a substrate. The substrate includes contact regions disposed over a major surface of the substrate and a dielectric layer disposed over the contact regions. The resist layer is disposed over the dielectric layer and the hole pattern includes through openings in the resist layer that are aligned with the contact regions. The through openings include a first through opening having a first critical dimension and a second through opening having a second critical dimension greater than the first critical dimension. The method includes modifying the hole pattern by depositing a material including silicon within the through openings by exposing the hole pattern to a first plasma generated from a gas mixture including SiCl4 and hydrogen, and then etching holes in the dielectric layer through the modified hole pattern, exposing the contact regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.