Flip chip bump with multi-PI opening
US11978713B2 · kind B2 · utility
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1References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 20, 2022 |
| Grant date | May 7, 2024 |
| Priority date | — |
| Expiry date | Jan 27, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01029
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure generally relates to a flip chip assembly having a bump that reduces stress levels in a low-k dielectric layer in the flip chip. Rather than having a single, large area plateau that interfaces with a large corresponding opening of an insulating layer in the flip chip, the bump includes a plurality of much smaller pillars that interface with a corresponding plurality of openings in the insulating layer. In so doing, the low-k layer within the flip chip experiences much less stress and hence, fewer failures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.