Erasable programmable single-ploy non-volatile memory cell and associated array structure
US11980029B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 9, 2022 |
| Grant date | May 7, 2024 |
| Priority date | — |
| Expiry date | Dec 29, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An erasable programmable single-poly non-volatile memory cell and an associated array structure are provided. The memory cell comprises a select transistor and a floating gate transistor. The floating gate of the floating gate transistor and an assist gate region are collaboratively formed as a capacitor. The floating gate of the floating gate transistor and an erase gate region are collaboratively formed as another capacitor. Moreover, the select transistor, the floating gate transistor and the two capacitors are collaboratively formed as a four-terminal memory cell. Consequently, the size of the memory cell is small, and the memory cell is operated more easily.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.